The mpeg2 encoder system is based on pc platform and data exchanging is based on pci bus 整個mpeg2編碼系統基于pc平臺,通過pci總線完成與計算機的通信。
This thesis consists of designing and implementing a jpeg encoder system that is compatiable with jpeg baseline mode using fpga ( field programmable gates array ) in standard hardware description language verilog 本文探討了以fpga ( fieldprogrammablegatesarray )為平臺,使用hdl ( hardwaredescriptionlanguage )語言設計并實現符合jpeg靜態圖象壓縮算法基本模式標準的圖象壓縮芯片。
Indicates the distance encoder system . when attached to the dynax 7 , 5 , 4 or 3l the d lens makes features such as adi ( advance distance integration ) flash metering possible with program flash 5600 hs ( d ) , 3600 hs ( d ) as well as with each respective camera s built - in flash 表示距離編碼系統將d鏡頭安裝在dynax7 、 dynax5或dynax3上時,不管配合programflash5600hs ( d ) 、 3600hs ( d )或各相機的內置閃燈,皆可使用如adi (先進綜合距離)閃燈測光等功能。